1
00:00:03,780 --> 00:00:09,193
Okay. So let's continue our exploration of
multiprocessor systems or small

2
00:00:09,193 --> 00:00:15,046
multiprocessor systems. And we left off
talking about concurrency and one of the

3
00:00:15,046 --> 00:00:21,046
things we talked about the end of class
or, or just a recap actually before we go

4
00:00:21,046 --> 00:00:26,460
there that let's, let's talk about
Sequential Consistency again as a model.

5
00:00:26,820 --> 00:00:32,235
So Sequential Consistency as a model
basically says that you have lots of

6
00:00:32,235 --> 00:00:38,016
different threads executing. And the
ordering of the memory references from the

7
00:00:38,016 --> 00:00:44,016
different threads to be inner leave but
everyone has to agree on what ordering is.

8
00:00:44,016 --> 00:00:49,846
And all the threads have to agree and see
the same ordering and the ordering of the

9
00:00:49,846 --> 00:00:54,317
loads in the stores in the respective
memory references have to be some valid

10
00:00:54,317 --> 00:00:58,845
ordering from the thread. So you can't
reorder within the thread. So if you have

11
00:00:58,845 --> 00:01:03,373
two threads and you have let's say try
four fingers here and each of your hand

12
00:01:03,373 --> 00:01:08,015
are for familiar references you can have
some inter leaving. You can have some

13
00:01:08,015 --> 00:01:12,314
other inter leaving. You can have that
inter leaving. You can have all these

14
00:01:12,314 --> 00:01:17,015
possible combinations leaving so what's
not valid is to have my two fingers sort

15
00:01:17,015 --> 00:01:21,014
of change order there and that is that's
sequentially consistent. Having said that,

16
00:01:21,014 --> 00:01:25,208
we talked about building processors up to
this point which are not do not maintain

17
00:01:25,208 --> 00:01:29,012
that order, so we talked about out of
order processors and out of order memory

18
00:01:29,012 --> 00:01:33,060
systems, which by definition are not doing
this sequentially consistent notion here.

19
00:01:33,060 --> 00:01:36,824
And if you want performance, as we talked
about, sometimes you want to move loads

20
00:01:36,824 --> 00:01:40,494
around, you want to push the load up so
you can get the, the operation out to the

21
00:01:40,494 --> 00:01:44,400
memory system early. You try to push the
store down because, you haven't computed

22
00:01:44,400 --> 00:01:48,070
the result yet, and you want to be able
to, sort of, compute the result before you

23
00:01:48,070 --> 00:01:51,693
go push it out to the memory system. So
these things fight against each other.

24
00:01:51,693 --> 00:01:55,364
Having a strict memory model, something
like sequential consistency, and having

25
00:01:55,505 --> 00:01:59,647
good performance. And in fact, you're
probably not going to find any processor

26
00:01:59,647 --> 00:02:04,742
which actually implements, true sequent
ial consistency. or. I'm trying to think.

27
00:02:04,742 --> 00:02:09,683
Maybe the, one of the, I, I, I, I don't
wanna say no because I'm, I, I have a

28
00:02:09,683 --> 00:02:15,182
hunch that the original, one of the
original shared memory processes, the RP3

29
00:02:15,182 --> 00:02:20,820
by IBM I believe might have had a very
strict memory model. But, besides that I

30
00:02:20,820 --> 00:02:28,136
don't think it had caches. most, most
things do not come even close to this. But

31
00:02:28,136 --> 00:02:32,865
we talk about sequencially consistent, or
sequencial consistency as a good model,

32
00:02:32,865 --> 00:02:37,652
because a programmer likes to think about
this. They like to think that when they

33
00:02:37,652 --> 00:02:42,440
write a piece of code what they execute
happens in order, and it happens in order

34
00:02:42,440 --> 00:02:48,504
relative to every other piece of code
happening on, on other threads. So, just

35
00:02:48,504 --> 00:02:53,416
to recap, what this ends up happening,
what this ends up doing is, sequencial

36
00:02:53,416 --> 00:02:58,394
consistency, we, we had talked about
having sort of ordering between loads in

37
00:02:58,394 --> 00:03:03,503
stores on the same processor before, and
you might, you can break that maybe if

38
00:03:03,503 --> 00:03:08,216
they're two different addresses. But
Sequential Consistency adds additional

39
00:03:08,216 --> 00:03:13,012
arcs in our dependency graph where every
memory instruction in one thread is

40
00:03:13,012 --> 00:03:17,684
dependence on all the previous memory
instructions. That's one way to reason

41
00:03:17,684 --> 00:03:22,854
about not reordering anything so if you
introduce all those arcs you are not going

42
00:03:22,854 --> 00:03:27,339
to accidentally break Sequential
Consistency. But sequential consistency

43
00:03:27,339 --> 00:03:32,260
says nothing about dependence from one
thread to another thread so there is no

44
00:03:32,260 --> 00:03:36,434
arc crossing between these two threads. So
hence you have all valid inter leaving