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Okay. So that finishes what I was talking
about, . And now we get to move onto a, a

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fun subject. And how to go about
implementing shared memory in a small

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symmetric multiprocessor. So to recap, the
multiprocessor has processors and memory.

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And all the processors are equidistant
away from the memory. Hence, the name,

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symmetric. you also have . And, . The
things here are fists, and graphics, and

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networks. And these also end up living on
your or your processor bus. Now, lets take

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a look at one of these processor buses.
And see, roughly, what, what one of these

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things looks like. So here, we have two
processors and some memory. It's all

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hanging off of a bus. And when I say a
bus, I actually mean a multi-prop bus. So

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any of these entities can drive different
wires. On this bus. Now, of course, you

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need to be careful here to not have
multiple entities driving the wires at the

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same time. And hence, you need some sort
of arbitration to prevent that. You could

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have a, pull down style bus. Where
multiple people can be trying to drive the

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bus at the same time. And nothing will set
on fire. Because there's basically, some

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sort of resistor which pulls the bus up to
a certain value. And then, when the entity

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wants to not assert anything onto the bus.
It just floats its output. Or when it

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wants to drive something on the bus, it'll
actually pull it down to value inside. So

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that'll be a zero pulled down and if it
doesn't drive anything, you just pull it

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out, point to y. But of course you can
have multi, multi-drop buses. And, I

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wanted to sorta talk a little bit about
arbitration for a bus. Cuz even if you

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have a multi-drop bus you still have
multiple people screaming on this bus at

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the same time. It's a shared medium. It's
like if everyone in this room were trying

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to scream at the same time. Trying to
communicate. . Figure out what's going on.

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And this is in contrast to sort of point
to point systems. which we will be talking

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about in a few lectures. Where we'll be
talking about other coherent systems that

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you can implement over switch networks.
But for right now let's assume that you

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just have a set of wires. Everyone can
basically drive these wires. Everyone can,

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receive from these wires. And usually,
arbitration actually is done as a pull

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down style bus. So let's, let's think real
hard, a couple ways how to do this. How,

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how do you do arbitration? people, once
you scream at the same time and say, I

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want the bus. Anyone have any thoughts?
So, , one way to do this, and this is

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actually relatively common for
arbitration, is you have . And, , let's

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say there are, . Your three request wires.
And then three grant wires. So, this is a,

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a valid way of going, doing this, and
actually this is not too uncommon. As to

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how it should, which has however many
requesters coming in, someone, search the

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request wire and. And a signal comes back
from the arbitrator check. And, In fact,

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in something like the PCIE or . There's a,
there's a, something that's very similar

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to this. There's a PCI post controller.
You, each device that's plugged into the

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multi drop bus pulls the wire down request
a bus. And within one cycle, the

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arbitrator makes a decision. And if you
have priority inside there, it could .

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There's different ways to go about doing
this. Today we'll assert one of the grant

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wires coming back and that's who wins the
arbitration. So that's one way to go about

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doing this. Another way is actually to
have a, let's say you have three different

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entities on this bus, you view it in a
more distributed fashion. You could have a

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multi-drop bus. And if you have three
entities, you actually have three wires on

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00:05:01,705 --> 00:05:06,793
your arbitration bus. And when someone
wants to use the bus, they just pull down.

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00:05:06,793 --> 00:05:12,062
And there's, there's pull up resistors.
What happens now is everyone can see who's

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00:05:12,062 --> 00:05:17,182
requesting at the same time and if you
have a fixed priority, let's say if all

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three wires are pulled down then question
one always wins or the lower number of one

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00:05:22,761 --> 00:05:27,946
always wins. You could do something like
that, so you can do it without having a

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00:05:27,946 --> 00:05:33,394
specific active entity you can dis tribute
fashion. So that's actually pretty common

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in some of these clusters and, and but you
also see this where there is operator

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00:05:38,645 --> 00:05:43,240
check if you want to do handsier
operation. Okay so let's split up our.

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From control here. So control is going to
be. I'm doing a load, or I'm doing a

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store. it's like a request. It's, it's ,
probably not actually, I'm doing a load

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and I'm doing a store. It's probably, load
and store are cut into smaller

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transactions. Like, as we'll, as we'll see
soon. Our protocols, there might be a

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request for a line or something like that.
Or a request to have exclusive access to

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data. And that will go across our control.
but it could also just be a load and

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restore. .... From the process of memory
is the same. There's addresses, there's

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some data, of course you hopefully your
probably not going to talk on your bus.

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You can do it when you talk but it's
probably what you don't want to do. Okay,

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so the easy contisioner of some multidrop
buses scream at the same time and whatever

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00:06:42,990 --> 00:06:49,740
you say on the bus everyone else hears.
One of the interesting things is that you

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may not want to... The bus, arbitrate the
bus, and then own the bus for a long

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period of time, and then release the bus.
Instead, you actually might want to

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pipeline these operations. So, such that,
you can be arbitrating for the next use of

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the bus while the current use of the bus
is currently still going on. So, to sort

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of show this graphically let's say this is
a transaction here for a close that

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Processor one is doing. So Processor one
puts on the arbitration bus, saying, I

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00:07:21,927 --> 00:07:28,877
want to use this bus sometime in the near
future. And it wins. Then, let's say it

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actually, the bus is designed so that each
subsequent cycle is, have, the, the next

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thing happen. So it's actually these four
cycles . Now. It's probably not this

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simple. But I kind of want to get the idea
across here that you can pipeline access

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00:07:52,078 --> 00:07:56,301
to the bus and be. And, and there's good
reason to do this. Because, for instance,

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00:07:56,301 --> 00:08:00,741
if you're trying to do a load from memory.
It takes time for the data to come back.

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00:08:00,741 --> 00:08:04,964
So the other option is you drive the
address. And, you just wait for the memory

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00:08:04,964 --> 00:08:09,132
to respond to the, to the load data or
something like that. But instead, if you

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00:08:09,132 --> 00:08:13,572
pipeline it, some other entity can start a
different transaction here. And you have

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00:08:13,572 --> 00:08:18,120
another transaction happening there on the
address bus. While you're waiting for the

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00:08:18,120 --> 00:08:21,285
memory to basically look up and get back.
Yeah.

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00:08:21,286 --> 00:08:28,861
So you'ld overlap nineteen pipeline buses.
one other thing I wanted to say is that

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this is a pretty simple pipe like bus
model. You can go to much more advance

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00:08:35,403 --> 00:08:41,514
things that are called split phase
transaction buses. Where what you'll

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00:08:41,514 --> 00:08:48,486
actually do is you'll basically arbitrate
for a bus, drive a request onto the bus,

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00:08:48,486 --> 00:08:55,868
and then the, the outcome of that may take
tens of cycles to release. meantime. And

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00:08:55,868 --> 00:09:01,005
the entity which has to respond, then,
rearbitrates for the , and gives the

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00:09:01,005 --> 00:09:06,142
response. So a good example of this is one
processor is trying to loot both the main

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00:09:06,142 --> 00:09:12,501
memory. very far away. It's going to take
hundreds of cycles to respond. So it the

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00:09:12,501 --> 00:09:17,088
bus. This load transaction, and the
address. And the transaction was designed

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00:09:17,088 --> 00:09:22,102
such that the bus, engineer designed it
such that data doesn't come back, in the

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00:09:22,102 --> 00:09:27,116
load transaction. Sometime in the future,
the memory controller, will arbitrate from

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00:09:27,116 --> 00:09:33,641
the bus . Well instead of having p1
arbitrate as the memory controller and it

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00:09:33,641 --> 00:09:38,424
will have something like load response.
And then load response will say maybe it

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00:09:38,424 --> 00:09:43,726
will the address. Maybe it won't. Probably
has to drive something here so that it

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00:09:43,726 --> 00:09:48,855
knows, so that the system knows which
response that it is memory transactions

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00:09:48,855 --> 00:09:53,926
happening. And then finally . So to sum up
here you can actually have multiple

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00:09:53,926 --> 00:09:59,228
transaction to the bus and have what we
think of as one transaction just a load

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00:09:59,228 --> 00:10:05,542
from memory actually split into multiple
transactions. They call the split paid

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00:10:05,542 --> 00:10:07,620
transaction .