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Okay, so now I'll start talking about,
we're gonna, we're gonna spend the rest of

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the lecture talking about different
coherence protocols, and relative merits

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of them, on a bus. I wanted to contrast
this to what we're gonna talk about in two

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lectures, where we're gonna be talking
about different coherence protocols across

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switch interconnects, and places where you
don't have a shared medium or a shared

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broadcast medium. Okay. So let's, as a
warm-up here, we're gonna start off by

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looking at what can happen with. We know
happen at the same time as memory

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transactions from a uni-processor. So,
let's take a look at where you can have

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consistency problems in a uni-processor
system. As a warm-up and a motivator here.

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So here, we have a processor, and that's a
cache. This is memory. And then, somewhere

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in the memory bus here, we off a bit with
a DMA agent. Or a direct memory access

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agent. Sometimes it's called, All
semester, even. Because it, it has a term,

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because of multiple agents which can
effectively drive transactions onto main

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memory clusters. So if you go look at
like, for instance, PCI Exu2014, PCI or

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PCI Express, which are sort of the
extension cards for your system, they'll,

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they'll use the term, bus mastering. What
that really means is that there's a DMA

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engine out at the I/O place. Okay, so,
what I'm trying to get across here is, you

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can actually. overlap in a uni-processor
system. Moving data from the disk to main

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memory without having to use the
processor. Because you have . Originally,

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or, or, . And require program to IO in
order to go access the disk. So a simple

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way the processor would actually read an
address, which is translated. And you

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don't have the here. Some . This impostor
and possibly . As you can tell that

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requires you to this memory. It's kinda
slow. So people decided let's put extra

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direct memory access engines out at diode
prices. So, this actually goes back to

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early, early computers. Like mainframes
like very sophisticated the, the, DMA. And

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they're, they're, they were, they're obvi
ously . System 360 they have, coviariable

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DMA engines that they can effectively .
But the simplest case given is basically

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going to have a register which says where
we provide disk and where memory and how

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long and, and a, and a go button, where
go, you could sit there . You could also

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possibly do it the other way. Okay, so
let's look at this from a coherence

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perspective. And let's choose this cache.
Let's look a memory to disk transaction.

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So we look we look at the DMA it should
say having this location in memory into

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this location of the disk. We tell it to
go. Now while it's doing that the

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processor writes to an address that tells
it to... Inside this page. What happens?

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It's not write through. There's no
coherence protocol really going on in this

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case so far. Well, values, hopefully. Or
maybe it does, these cache lines do out to

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main memory. So then it gets some of the
new values, and some of the old values.

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The point I'm trying to make here is that,
you don't know. And what's gonna happen?

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and that, that's a little scary. You
wanna, you know? You wanna in your system.

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Now, you can say, well maybe the
processors shouldn't go and write to that,

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those memory addresses. That is a valid
solution. this is actually pretty common

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on, on modern day systems. Is that the OS
will know when the actually is in flight.

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They will just make sure not to go access
that, those memory addresses. Well, what I

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was trying to introduce here is that you
actually processor system, can have

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coherence problems, with respect to. Where
the different addresses are. You can

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actually have . . You can also have it
going the other way. To the disks to main

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memory transferring in that direction.
Well, let's say there's some values in the

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cache of the CPU. This is actually
probably the more interesting case, is

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that you have some data in the CPU's
cache, erasing the disk to physical

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memory. But all of a sudden, the CPU's
cache. Doesn't pick up the new value. And

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it wants to go and read that. It's like
reading a file off a disk or some thing.

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This is gonna get the wrong value. So this
introduces, this moves us to our first

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idea in our coherence protocols, that has
a funny name, called snoopy caches. no,

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this is not named for the, the dog in the
Peanuts cartoons. But instead, Stu Goodman

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and, I believe it's a professor now and
one of his students, came up with the idea

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that you have the cash on the what's going
on and effectively update the cash with

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the, the data that's flying by on the bus.
So, if we look at this from a little bit

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more harder perspective. . We have our
cache and we have the tags. And escape

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into the cache. And it is effectively
sitting there watching the bus. And if a

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address that is in the cache slides behind
the bus, it needs to do something about

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it. It probably needs to invalidate the
address if its a right occurring across

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the bus. You can also do it the other way
that if you have a DNA engine which is

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reading from a memory and the data is
dirty in cache and it's not a memory, it's

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a right back cache, it may need to provide
data to the, the I O device that's trying

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to read from a memory and override
effectively where its coming from main

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memory. Now it probably doesn't wanna try
that after you're on the bus but there's

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also arbitration that's actually, actually
happening there. To determine who has the

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actual data. . But you have to figure out
sort of what is, what is the right

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fitting? You know, we're talking a little
bit more in today's lecture, what is the

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right thing to do in these, these
interesting formative cases? Before we

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move on here, this, this is getting a
little bit hard. maybe back in 1983, this

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wasn't so bad. But nowadays, we just tags
and our . A dual coordinate.'Cause in the

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Snoopy protocol, we're gonna need all
possible memory, transactions that are

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going on, let's say, by one processor.
And/or and DMA engine, to be verified by

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every other processor entity in the
system. That's a fair amount of bandwidth

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coming into here. And you could add two
ports to that. And that's okay if the

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cache is sort of f arther out. But it
might slow down your cache . Level one

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cache. So typically the way that people
build this is they'll try to maybe move

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forward or snoop on a level two cache and
have level one cache which is not

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necessarily snooped. Now this is where we
get back to inclusive versus exclusive

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caches. If you're level two cache is
inclusive of all data in level one this is

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actually not so bad to do. Because you are
guaranteed to the tags in level two cache.

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Global one Cash. So, you don't have to go,
move all the way down for cash. If you use

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exclusive cash, well, life gets a lot
harder. Cuz basically you need a check

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with a Global one emblem to . so, anyways,
all I was trying to get across here's that

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this, this significantly increases the
price of or cash design here, your tab

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design as you add more portions to this.
And it's not actually an area question, I

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mean. Just makes it larger, puts more of,
a clock cycle perfomance, specially if

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it's, your global one captioning, where
two important task. That's a critical

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tacking your processor to go, and certain
one, two, and anything else that too. One

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ways all this is actually, you have a
unique, ported tax structure and you

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somehow delay, the rest of, the, catch
soup transaction, while, you arbitrate and

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wait for time, in order to go access the
tax. So you. But you can, multiplex let's

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say the, the one portion of the tag, every
other cycle. One cycle's the main

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processor. One cycle is for the
transaction.

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. So just, have a little more of block
diagram view of this. We have a bus, of

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multi-processors, and our snoopy cache,
which actually has to see, all of the,

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items. No traffic. And in all the main
processor traffic across this bus. So

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that's a, a lot of bandwidth because
essentially you're broadcasting... Well,

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you might have to broadcast all of your
actions from one processor to all the, all

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the other processors. But we're looking at
techniques to reduce the requirements of,

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of this broadcast to be the subset of, of
the data. Okay so questions so far? , and,

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and adding supports before going into
protocols.