Index of /学校网课和考研/Computer Architecture计算机体系结构-prinstone/Videos

[ICO]NameLast modifiedSizeDescription
[PARENTDIR]Parent Directory  -  
[TXT]095_L19S3 - Message Passing (26 -59).srt2022-05-16 12:29 32K 
[TXT]075_L15S3 - GPUs (20 -02).srt2022-05-16 12:30 24K 
[TXT]034_L7S4 - Register Renaming with Values in IQ and ROB (12 -14).srt2022-05-16 12:30 15K 
[TXT]072_L14S6 - Vector Software and Compiler Optimizations (5 -54).srt2022-05-16 12:31 7.0K 
[TXT]045_L9S5 - Dynamic Events and Clustered VLIWs (10 -42).srt2022-05-16 12:34 15K 
[TXT]087_L17S5 - Dekker's Algorithm (14 -13).srt2022-05-16 12:34 15K 
[TXT]101_L20S5 - Routing and Flow Control (20 -27).srt2022-05-16 12:35 25K 
[TXT]035_L7S5 - Memory Disambiguation (9 -49).srt2022-05-16 12:37 12K 
[TXT]004_L1S4 - Architecture and Microarchitecture (23 -37).srt2022-05-16 12:38 31K 
[TXT]050_L10S4 - Dynamic Outcome Prediction (29 -12).srt2022-05-16 12:38 37K 
[TXT]083_L17S1 - Sequential Consistency Review (3 -48).srt2022-05-16 12:39 5.1K 
[TXT]098_L20S2 - Topology (18 -53).srt2022-05-16 12:41 21K 
[TXT]012_L3S1 - Control Hazards, Jumps (15 -56).srt2022-05-16 12:41 21K 
[TXT]046_L9S6 - Case Study - IA-64 -Itanium (21 -10).srt2022-05-16 12:42 28K 
[TXT]068_L14S2 - Cache and Memory Protection Interaction (22 -18).srt2022-05-16 12:42 27K 
[TXT]005_L1S5 - Machine Models (16 -02).srt2022-05-16 12:42 21K 
[TXT]081_L16S3 - Sequential Consistency (21 -00).srt2022-05-16 12:43 19K 
[TXT]058_L12S1 - Multiporting and Banking (20 -08).srt2022-05-16 12:45 25K 
[TXT]048_L10S2 - Branch Prediction Introduction (5 -18).srt2022-05-16 12:45 6.8K 
[TXT]060_L12S3 - Non-blocking Caches (19 -29).srt2022-05-16 12:46 27K 
[TXT]084_L17S2 - Locks and Semaphores (10 -01).srt2022-05-16 12:46 12K 
[TXT]089_L18S2 - Bus Implementation (10 -12).srt2022-05-16 12:49 12K 
[TXT]094_L19S2 - Introduction to Interconnection Networks (8 -29).srt2022-05-16 12:49 11K 
[TXT]028_L6S3 - I2O1 Processors (28 -44).srt2022-05-16 12:49 37K 
[TXT]039_L8S4 - Classic VLIW Challenges (8 -18).srt2022-05-16 12:50 11K 
[TXT]017_L4S1 - Classifying Caches (28 -07).srt2022-05-16 12:51 38K 
[TXT]065_L13S4 - Translation and Protection (14 -37).srt2022-05-16 12:51 19K 
[TXT]042_L9S2 - Review of Predication (30 -48).srt2022-05-16 12:52 40K 
[TXT]043_L9S3 - Predication Implementation (10 -06).srt2022-05-16 12:52 11K 
[TXT]077_L15S5 - Course-Grain Multithreading (26 -16).srt2022-05-16 12:52 32K 
[TXT]015_L3S4 - Memory Technologies (22 -47).srt2022-05-16 12:52 29K 
[TXT]071_L14S5 - Vector Hardware Optimizations (18 -52).srt2022-05-16 12:54 23K 
[TXT]002_L1S2 - Motivation (16 -40).srt2022-05-16 12:54 23K 
[TXT]102_L21S1 - Credit Based Flow Control (7 -23).srt2022-05-16 12:54 9.9K 
[TXT]104_L21S3 - False Sharing (9 -29).srt2022-05-16 12:54 10K 
[TXT]103_L21S2 - Deadlock (10 -09).srt2022-05-16 12:55 13K 
[TXT]033_L7S3 - Register Renaming with Pointers to IQ and ROB (24 -54).srt2022-05-16 12:55 33K 
[TXT]014_L3S3 - Control Hazards, Others(7 -51).srt2022-05-16 12:56 9.5K 
[TXT]106_L21S5 - Implementation (29 -02).srt2022-05-16 12:57 36K 
[TXT]006_L1S6 - ISA Characteristics (25 -47).srt2022-05-16 12:57 35K 
[VID]007_L1S7 - Recap (01 -17).mp42022-05-16 12:57 1.9M 
[TXT]007_L1S7 - Recap (01 -17).srt2022-05-16 12:57 1.4K 
[TXT]013_L3S2 - Control Hazards, Branch (24 -02).srt2022-05-16 12:58 29K 
[TXT]037_L8S2 - Introduction to VLIW (21 -57).srt2022-05-16 12:58 25K 
[TXT]091_L18S4 - Bus-Based Multiprocessors (12 -09).srt2022-05-16 12:58 12K 
[TXT]029_L6S4 - IO3 Processors (16 -23).srt2022-05-16 12:59 21K 
[TXT]070_L14S4 - Vector Parallelism (6 -44).srt2022-05-16 12:59 7.8K 
[TXT]030_L6S5 - IO2I Processors (4 -31).srt2022-05-16 13:00 5.7K 
[TXT]032_L7S2 - Register Renaming Introduction (11 -08).srt2022-05-16 13:01 15K 
[TXT]051_L10S5 - Target Address Prediction (18 -45).srt2022-05-16 13:01 23K 
[TXT]086_L17S4 - Memory Fences (11 -11).srt2022-05-16 13:02 13K 
[VID]003_L1S3 - Course Content (9 -10).mp42022-05-16 13:02 26M 
[TXT]003_L1S3 - Course Content (9 -10).srt2022-05-16 13:02 12K 
[TXT]073_L15S1 - Reduction, Scatter -Gather, and the Cray 1 (9 -20).srt2022-05-16 13:02 12K 
[TXT]016_L3S5 - Motivation for Caches (22 -25).srt2022-05-16 13:02 31K 
[TXT]040_L8S5 - Introduction to Predication (9 -51).srt2022-05-16 13:03 12K 
[TXT]055_L11S4 - Multilevel Caches (17 -37).srt2022-05-16 13:03 21K 
[VID]029_L6S4 - IO3 Processors (16 -23).mp42022-05-16 13:03 32M 
[TXT]001_L1S1 - Course Overview (4 -34).srt2022-05-16 13:04 6.3K 
[VID]074_L15S2 - SIMD (6 -58).mp42022-05-16 13:05 15M 
[TXT]074_L15S2 - SIMD (6 -58).srt2022-05-16 13:05 8.1K 
[TXT]023_L5S2 - Interrupts and Bypassing (12 -13).srt2022-05-16 13:06 17K 
[TXT]066_L13S5 - TLB Processing (12 -00).srt2022-05-16 13:06 15K 
[TXT]009_L2S2 - Pipeline Basics (30 -51).srt2022-05-16 13:06 42K 
[TXT]079_L16S1 - SMT Implementation (17 -19).srt2022-05-16 13:07 22K 
[TXT]053_L11S2 - Cache Pipelining (14 -16).srt2022-05-16 13:07 16K 
[TXT]049_L10S3 - Static Outcome Prediction (16 -05).srt2022-05-16 13:07 20K 
[TXT]105_L21S4 - Introduction to Directory Coherence (12 -55).srt2022-05-16 13:08 16K 
[TXT]093_L19S1 - More Cache Coherence Protocols - (21 -16).srt2022-05-16 13:08 26K 
[TXT]080_L16S2 - Introduction to Parallelism (17 -59).srt2022-05-16 13:09 20K 
[TXT]056_L11S5 - Victim Caches (6 -04).srt2022-05-16 13:09 6.9K 
[TXT]025_L5S4 - Introduction to Out-of-Order Processors (30 -53).srt2022-05-16 13:10 40K 
[TXT]011_L2S4 - Data Hazards (46 -33).srt2022-05-16 13:10 58K 
[TXT]047_L10S1 - Branch Cost Motivation (6 -37).srt2022-05-16 13:10 9.2K 
[VID]061_L12S4 - Critical Word First and Early Restart (3 -06).mp42022-05-16 13:11 7.0M 
[TXT]061_L12S4 - Critical Word First and Early Restart (3 -06).srt2022-05-16 13:11 4.0K 
[TXT]067_L14S1 - Address Translation Review (9 -36).srt2022-05-16 13:11 14K 
[TXT]038_L8S3 - VLIW Compiler Optimizations (21 -20).srt2022-05-16 13:12 25K 
[VID]001_L1S1 - Course Overview (4 -34).mp42022-05-16 13:13 19M 
[TXT]099_L20S3 - Strutural Hazards (10 -13).srt2022-05-16 13:15 12K 
[TXT]020_L4S4 - Basic Two-way In-order Superscalar (4 -56).srt2022-05-16 13:16 6.7K 
[TXT]059_L12S2 - Software Memory Optimizations (16 -53).srt2022-05-16 13:17 32K 
[TXT]063_L13S2 - Base and Bound Registers (11 -44).srt2022-05-16 13:18 15K 
[VID]056_L11S5 - Victim Caches (6 -04).mp42022-05-16 13:19 13M 
[VID]105_L21S4 - Introduction to Directory Coherence (12 -55).mp42022-05-16 13:19 23M 
[VID]099_L20S3 - Strutural Hazards (10 -13).mp42022-05-16 13:20 23M 
[VID]043_L9S3 - Predication Implementation (10 -06).mp42022-05-16 13:20 24M 
[VID]030_L6S5 - IO2I Processors (4 -31).mp42022-05-16 13:22 8.1M 
[TXT]022_L5S1 - Baseline Superscalar and Alignment (4 -16).srt2022-05-16 13:22 5.7K 
[TXT]008_L2S1 - Microcoded Microarchitecture (14 -08).srt2022-05-16 13:22 20K 
[VID]084_L17S2 - Locks and Semaphores (10 -01).mp42022-05-16 13:23 19M 
[VID]016_L3S5 - Motivation for Caches (22 -25).mp42022-05-16 13:23 44M 
[TXT]078_L15S6 - Simultaneous Multithreading (12 -53).srt2022-05-16 13:24 14K 
[VID]004_L1S4 - Architecture and Microarchitecture (23 -37).mp42022-05-16 13:24 53M 
[TXT]036_L8S1 - Limits of Out-of-Order Design Complexity (13 -13).srt2022-05-16 13:24 18K 
[TXT]027_L6S2 - I2O2 Processors (19 -58).srt2022-05-16 13:25 25K 
[VID]041_L9S1 - Scheduling Model Review (5 -58).mp42022-05-16 13:25 20M 
[TXT]041_L9S1 - Scheduling Model Review (5 -58).srt2022-05-16 13:25 7.0K 
[TXT]019_L4S3 - Superscalar 1 (6 -42).srt2022-05-16 13:26 8.7K 
[VID]020_L4S4 - Basic Two-way In-order Superscalar (4 -56).mp42022-05-16 13:26 9.5M 
[TXT]018_L4S2 - Cache Performance (17 -11).srt2022-05-16 13:29 22K 
[VID]079_L16S1 - SMT Implementation (17 -19).mp42022-05-16 13:30 33M 
[TXT]090_L18S3 - Cache Coherence (12 -25).srt2022-05-16 13:31 12K 
[TXT]057_L11S6 - Prefetching (12 -34).srt2022-05-16 13:32 15K 
[TXT]100_L20S4 - Network Performance (15 -35).srt2022-05-16 13:33 18K 
[VID]087_L17S5 - Dekker's Algorithm (14 -13).mp42022-05-16 13:34 29M 
[VID]026_L6S1 - Review of Out-of-Order Processors (3 -26).mp42022-05-16 13:34 6.9M 
[TXT]026_L6S1 - Review of Out-of-Order Processors (3 -26).srt2022-05-16 13:34 4.5K 
[VID]027_L6S2 - I2O2 Processors (19 -58).mp42022-05-16 13:34 39M 
[VID]031_L7S1 - Speculation and Branch (14 -37).mp42022-05-16 13:35 29M 
[TXT]031_L7S1 - Speculation and Branch (14 -37).srt2022-05-16 13:35 19K 
[VID]032_L7S2 - Register Renaming Introduction (11 -08).mp42022-05-16 13:35 22M 
[VID]104_L21S3 - False Sharing (9 -29).mp42022-05-16 13:35 15M 
[VID]035_L7S5 - Memory Disambiguation (9 -49).mp42022-05-16 13:36 18M 
[TXT]085_L17S3 - Atomic Operations (27 -11).srt2022-05-16 13:36 32K 
[VID]075_L15S3 - GPUs (20 -02).mp42022-05-16 13:36 45M 
[VID]054_L11S3 - Write Buffers (9 -52).mp42022-05-16 13:36 22M 
[TXT]054_L11S3 - Write Buffers (9 -52).srt2022-05-16 13:36 12K 
[VID]055_L11S4 - Multilevel Caches (17 -37).mp42022-05-16 13:36 33M 
[VID]090_L18S3 - Cache Coherence (12 -25).mp42022-05-16 13:36 21M 
[TXT]062_L13S1 - Memory Management Introduction (13 -04).srt2022-05-16 13:37 18K 
[VID]049_L10S3 - Static Outcome Prediction (16 -05).mp42022-05-16 13:37 29M 
[VID]066_L13S5 - TLB Processing (12 -00).mp42022-05-16 13:37 26M 
[VID]107_L21S6 - Scalability of Directory Coherence (13 -31).mp42022-05-16 13:37 24M 
[TXT]107_L21S6 - Scalability of Directory Coherence (13 -31).srt2022-05-16 13:37 17K 
[VID]095_L19S3 - Message Passing (26 -59).mp42022-05-16 13:37 49M 
[VID]072_L14S6 - Vector Software and Compiler Optimizations (5 -54).mp42022-05-16 13:37 12M 
[VID]012_L3S1 - Control Hazards, Jumps (15 -56).mp42022-05-16 13:38 27M 
[TXT]064_L13S3 - Page Based Memory Systems (27 -04).srt2022-05-16 13:38 33K 
[VID]065_L13S4 - Translation and Protection (14 -37).mp42022-05-16 13:38 34M 
[TXT]044_L9S4 - Speculation Execution (26 -02).srt2022-05-16 13:38 35K 
[VID]045_L9S5 - Dynamic Events and Clustered VLIWs (10 -42).mp42022-05-16 13:38 23M 
[VID]080_L16S2 - Introduction to Parallelism (17 -59).mp42022-05-16 13:38 35M 
[VID]047_L10S1 - Branch Cost Motivation (6 -37).mp42022-05-16 13:38 12M 
[VID]098_L20S2 - Topology (18 -53).mp42022-05-16 13:38 40M 
[VID]067_L14S1 - Address Translation Review (9 -36).mp42022-05-16 13:38 23M 
[VID]057_L11S6 - Prefetching (12 -34).mp42022-05-16 13:39 25M 
[VID]024_L5S3 - Interrupts and Exceptions (29 -25).mp42022-05-16 13:39 57M 
[TXT]024_L5S3 - Interrupts and Exceptions (29 -25).srt2022-05-16 13:39 41K 
[VID]068_L14S2 - Cache and Memory Protection Interaction (22 -18).mp42022-05-16 13:39 55M 
[VID]044_L9S4 - Speculation Execution (26 -02).mp42022-05-16 13:39 49M 
[VID]085_L17S3 - Atomic Operations (27 -11).mp42022-05-16 13:39 51M 
[VID]091_L18S4 - Bus-Based Multiprocessors (12 -09).mp42022-05-16 13:40 24M 
[VID]088_L18S1 - Locking Review (1 -56).mp42022-05-16 13:40 4.3M 
[TXT]088_L18S1 - Locking Review (1 -56).srt2022-05-16 13:40 2.1K 
[VID]089_L18S2 - Bus Implementation (10 -12).mp42022-05-16 13:40 18M 
[VID]002_L1S2 - Motivation (16 -40).mp42022-05-16 13:40 43M 
[TXT]082_L16S4 - Introduction to Locks (03 -39).srt2022-05-16 13:41 4.0K 
[VID]083_L17S1 - Sequential Consistency Review (3 -48).mp42022-05-16 13:41 8.5M 
[VID]005_L1S5 - Machine Models (16 -02).mp42022-05-16 13:41 33M 
[VID]037_L8S2 - Introduction to VLIW (21 -57).mp42022-05-16 13:41 42M 
[VID]025_L5S4 - Introduction to Out-of-Order Processors (30 -53).mp42022-05-16 13:41 62M 
[VID]050_L10S4 - Dynamic Outcome Prediction (29 -12).mp42022-05-16 13:41 54M 
[VID]101_L20S5 - Routing and Flow Control (20 -27).mp42022-05-16 13:42 48M 
[VID]100_L20S4 - Network Performance (15 -35).mp42022-05-16 13:42 32M 
[VID]033_L7S3 - Register Renaming with Pointers to IQ and ROB (24 -54).mp42022-05-16 13:42 50M 
[VID]060_L12S3 - Non-blocking Caches (19 -29).mp42022-05-16 13:42 42M 
[VID]102_L21S1 - Credit Based Flow Control (7 -23).mp42022-05-16 13:42 14M 
[VID]015_L3S4 - Memory Technologies (22 -47).mp42022-05-16 13:42 50M 
[TXT]076_L15S4 - Multithreading Motivation (7 -33).srt2022-05-16 13:43 9.0K 
[VID]034_L7S4 - Register Renaming with Values in IQ and ROB (12 -14).mp42022-05-16 13:43 24M 
[VID]018_L4S2 - Cache Performance (17 -11).mp42022-05-16 13:43 31M 
[VID]086_L17S4 - Memory Fences (11 -11).mp42022-05-16 13:43 23M 
[VID]028_L6S3 - I2O1 Processors (28 -44).mp42022-05-16 13:43 55M 
[VID]019_L4S3 - Superscalar 1 (6 -42).mp42022-05-16 13:43 13M 
[VID]017_L4S1 - Classifying Caches (28 -07).mp42022-05-16 13:43 57M 
[VID]092_L18S5 - Cache Coherence Protocols (33 -22).mp42022-05-16 13:43 64M 
[TXT]092_L18S5 - Cache Coherence Protocols (33 -22).srt2022-05-16 13:43 37K 
[VID]093_L19S1 - More Cache Coherence Protocols - (21 -16).mp42022-05-16 13:43 42M 
[VID]096_L19S4 - Interconnect Design (15 -06).mp42022-05-16 13:43 29M 
[TXT]096_L19S4 - Interconnect Design (15 -06).srt2022-05-16 13:43 18K 
[VID]097_L20S1 - Networking Review (7 -56).mp42022-05-16 13:43 19M 
[VID]062_L13S1 - Memory Management Introduction (13 -04).mp42022-05-16 13:43 32M 
[VID]059_L12S2 - Software Memory Optimizations (16 -53).mp42022-05-16 13:43 71M 
[VID]021_L4S5 - Fetch Logic and Alignment (11 -01).mp42022-05-16 13:43 19M 
[TXT]021_L4S5 - Fetch Logic and Alignment (11 -01).srt2022-05-16 13:43 14K 
[VID]022_L5S1 - Baseline Superscalar and Alignment (4 -16).mp42022-05-16 13:43 8.5M 
[VID]063_L13S2 - Base and Bound Registers (11 -44).mp42022-05-16 13:43 26M 
[VID]082_L16S4 - Introduction to Locks (03 -39).mp42022-05-16 13:43 7.3M 
[TXT]052_L11S1 - Basic Cache Optimizations (16 -08).srt2022-05-16 13:44 22K 
[VID]053_L11S2 - Cache Pipelining (14 -16).mp42022-05-16 13:44 28M 
[VID]010_L2S3 - Structural Hazard (10 -13).mp42022-05-16 13:44 23M 
[TXT]010_L2S3 - Structural Hazard (10 -13).srt2022-05-16 13:44 12K 
[VID]011_L2S4 - Data Hazards (46 -33).mp42022-05-16 13:44 93M 
[VID]103_L21S2 - Deadlock (10 -09).mp42022-05-16 13:44 19M 
[VID]064_L13S3 - Page Based Memory Systems (27 -04).mp42022-05-16 13:44 62M 
[VID]023_L5S2 - Interrupts and Bypassing (12 -13).mp42022-05-16 13:44 24M 
[VID]077_L15S5 - Course-Grain Multithreading (26 -16).mp42022-05-16 13:44 60M 
[VID]073_L15S1 - Reduction, Scatter -Gather, and the Cray 1 (9 -20).mp42022-05-16 13:44 23M 
[VID]051_L10S5 - Target Address Prediction (18 -45).mp42022-05-16 13:44 36M 
[VID]048_L10S2 - Branch Prediction Introduction (5 -18).mp42022-05-16 13:44 9.4M 
[VID]036_L8S1 - Limits of Out-of-Order Design Complexity (13 -13).mp42022-05-16 13:44 26M 
[VID]081_L16S3 - Sequential Consistency (21 -00).mp42022-05-16 13:44 41M 
[VID]038_L8S3 - VLIW Compiler Optimizations (21 -20).mp42022-05-16 13:44 40M 
[VID]069_L14S3 - Vector Processor Introduction (18 -04).mp42022-05-16 13:44 45M 
[TXT]069_L14S3 - Vector Processor Introduction (18 -04).srt2022-05-16 13:44 24K 
[VID]070_L14S4 - Vector Parallelism (6 -44).mp42022-05-16 13:44 14M 
[VID]014_L3S3 - Control Hazards, Others(7 -51).mp42022-05-16 13:44 16M 
[VID]052_L11S1 - Basic Cache Optimizations (16 -08).mp42022-05-16 13:44 34M 
[VID]006_L1S6 - ISA Characteristics (25 -47).mp42022-05-16 13:44 58M 
[VID]078_L15S6 - Simultaneous Multithreading (12 -53).mp42022-05-16 13:44 30M 
[VID]042_L9S2 - Review of Predication (30 -48).mp42022-05-16 13:44 73M 
[VID]039_L8S4 - Classic VLIW Challenges (8 -18).mp42022-05-16 13:45 16M 
[VID]040_L8S5 - Introduction to Predication (9 -51).mp42022-05-16 13:45 19M 
[VID]008_L2S1 - Microcoded Microarchitecture (14 -08).mp42022-05-16 13:45 38M 
[VID]076_L15S4 - Multithreading Motivation (7 -33).mp42022-05-16 13:45 16M 
[VID]009_L2S2 - Pipeline Basics (30 -51).mp42022-05-16 13:45 65M 
[VID]013_L3S2 - Control Hazards, Branch (24 -02).mp42022-05-16 13:45 48M 
[VID]046_L9S6 - Case Study - IA-64 -Itanium (21 -10).mp42022-05-16 13:45 49M 
[VID]094_L19S2 - Introduction to Interconnection Networks (8 -29).mp42022-05-16 13:45 15M 
[VID]106_L21S5 - Implementation (29 -02).mp42022-05-16 13:45 57M 
[VID]071_L14S5 - Vector Hardware Optimizations (18 -52).mp42022-05-16 13:45 42M 
[VID]058_L12S1 - Multiporting and Banking (20 -08).mp42022-05-16 13:45 49M 
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